1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a device structure.
2. Description of the Related Art
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated Circuit (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction in the size of a device. The nonvolatile memories include various types of devices. Different types of devices have been developed for specific applications' requirements in each of these segments. The formation of nonvolatile memories toward the trends of low supply power and fast access, because these requirements are necessary for the application of the mobile computing system.
One of the semiconductor devices is called anti-fuse as shown in FIG. 1. The MOS transistor consists of a silicon substrate 100, a gate dielectric 104, a doped polysilicon gate 105, lightly doped regions 103, and source/drain regions 101 formed by diffusion of N-type dopants in the silicon substrate. Silicide 107 is introduced on the exposed surface of the top portion of the gate 105 and the source and drain regions 101. The gate dielectric 104 separating the polysilicon gate 105 from the channel region usually consists of the thermally grown silicon dioxide. When the gate dielectric is stressed beyond a critical electrical field, the transistor is destroyed by rupturing of the gate dielectric. Rupturing dielectric requires sufficient pulse width duration and amplitude to provide enough damaging power through the gate oxide, which therefore produces a reliable, low resistance anti-fuse.
The anti-fuse layer is initially intact, but it can be ruptured or broken by applying a sufficient voltage across the memory cell. The voltage is chosen such that the anti-fuse layer ruptures, and a high conductivity state of the memory cell is established.
In reading operation, a ground voltage is applied to the transistor's body or well via metal interconnect, and a read voltage is applied to the gate. In this situation, the gate oxide between well and gate is stressed in a low electric field, thereby allowing no current to flow between the well and the gate. Since no reading current is detected, the digital state is defined as “0”. To program anti-fuse, the gate voltage is increased until avalanche breakdown occurs at the gate oxide. When avalanche breakdown occurs, a breakdown current will flow through the oxide. This current flow causes permanent damages in the oxide structure along the path of the breakdown current. When the gate is applied with a read voltage, there is a significant leakage current to flow between the well and the gate. As a result, the digital state is defined as “1” by this reading current.
FIG. 2 illustrates other alternative programming mechanisms including “Localized gate oxide breakdown”, “Drain junction breakdown” and “Source/Drain punch through” used for Anti-Fuse applications. However, all these three mechanisms are required a high drain voltage, Vd, for programming while the Vg, Vs and body are grounded. As Vd is increased and applied to the drain, one of the three programming mechanisms will take place first. The first mechanism is determined by the operating and device parameters, such as applied signal timing, signal amplitude, gate oxide thickness, channel length, doping concentration, fringing capacitance and so forth. By leaving Vg as floating, the localized gate oxide breakdown can be avoided for the high Vd potential. However, the high Vd induces a moderate potential in Vg which therefore has the risk to turns on the channel.
FIG. 3 illustrates the overlapped and fringing capacitors, i.e. COV and CFR, near the drain side. The total coupling capacitance includes COV and CFR. The Vg can be induced to a moderate voltage between ground and Vd depending on its gate coupling efficiency. Once Vg approaches the transistor's threshold voltage, the channel has been lightly turned on and allows high current during its programming stage. Therefore, the anti-fuse devices in the prior art have found high power consumption and gate oxide degradation problems due to their high coupling capacitance. An anti-fuse device having low coupling capacitance is needed to prevent localized gate oxide breakdown and channel turned-on for low power and high density applications.
Those devices are manufactured by various processes and the device operating scheme is different from each other. The present invention provides a basic device structure for those devices including, but not limited to, non-volatile, anti-fuse, mask-ROM.